资源列表
DDS
- 用FPGA实现数字频率合成的源程序，ALTERA公司芯片。-A DDS program with Altera chip.
FirDec
- 用FPGA实现FIR抽取器源程序，用于数字下变频。-A program to realize FIR DEC.
chengfa
- 可编程器件已有很久的发展历史了，其功能之卓越和成熟已经令当今的电子工程师们赞叹不已，除了它体积小、容量大、I/O口丰富、易编程和加密等优点外，更突出的特点是其芯片的在系统可编程技术。四位乘法器程序,VHDL语言,仿真图形 开发-four process
freg
- freg goes throught the road by finite machine(include Verilog code and test bench)
turbo
- Turbo仿真。VHDL语言。对学习编码很有帮助-Turbo
edapinluji
- 接通电源，可以测输入的频率，显示在数码管上。-Switch on the power, you can measure the input frequency, displayed on the digital pipe.
caideng
- 几路彩灯可以在程序的控制下彩灯轮流点亮，并可改变点亮的顺序。-Can process several road lantern lights turn under the control of light, light can change the order.
DWT-VHDL
- 小波变换的VHDL代码，内带正变换逆变换的测试文件。-Wavelet transform VHDL code, with a positive transformation within the inverse transform of the test file.
mul8b
- 有VerilogHDL编写的8位乘法器，可以综合。-Have been prepared in 8-bit multiplier VerilogHDL can be integrated.
VerilogHDLTeach
- VHDL语言教程，内附代码和综合出的电路图-VHDL Language Guide contains the code and integrated circuit out of
crc5
- 用VerilogHDL编写的CRC5校验，可以综合。-Check with VerilogHDL CRC5 prepared, can be summarized.
send
- 用VerilogHDL编写的串口发送模块，可以综合。-VerilogHDL prepared using serial transmission module, can be integrated.