资源列表
dds5.0
- DDS电源设计，使用时须将SIN_ROM.VHD中的LPM_FILE修改为个人MIF文件的路径，本套程序中包含多个MIF文件，注意选用合适的文件。-DDS power supply design, use of LPM_FILE SIN_ROM.VHD shall modify the path for personal MIF file, this set of procedures in multiple MIF files, pay attention to choose the appr
74ls109
- 74ls109电路的VERILOG源代码，已经验证-74ls109 circuit
74ls138
- 74ls138电路的verilog源代码，已经验证。-74ls138 circuit verilog
74ls165
- 74ls165电路源代码verilog,已经验证。-74ls165 verilog
p4_adder.tar
- 用vhdl实现的P4加法器，包括主要元件rca加法器，carry select adder,pg模块，并提供了一个测试文件，用modelsim测试通过-P4 adder implemented using VHDL, including the major component such as: rca adder, carry select adder, pg module,in addition provides a test file, all modules have been teste
my_clock
- 使用verilog HDL语言编写的时钟电路代码，能实现24小时电子钟的功能。-Using verilog HDL code written in the clock circuit can achieve 24-hour clock function.
timer
- 外设timer设计：16bit定时器、ETU计数器、具有3种可配置中断请求输出、内部寄存器的读写编程。-Peripheral timer design: 16bit timer, ETU counter, with 3 configurable interrupt request output, the internal register read and write programming.
auart_send
- usb command 静态存储器源程序-usb command
my_walkled_v3
- 自动跑马灯 开发板采用stratix4系列开发板 可以使用开关控制跑马灯方向-LED WALKING
c3
- VerilogHDL编写的8位加法器实现-bgfhgfhjgjhgj
FPGAExamples
- 列举了一些FPGA的常用实例，有助于加深对FPGA的了解-gfdhgfhgfdgvfhgfhgjngh
p_s
- 用Verilog HDL语言进行串并转换，并通过Quartus Ⅱ 功能仿真验证-Series with the Verilog HDL language and converted, and through functional simulation Quartus Ⅱ