资源列表
SafeUSB
- 加法器 將A+B16BITS 相加 請多多利用-adder加法器 將A+B16BITS 相加 請多多利用
verilog_exsample
- verilog入门学习代码，保证让你一看就会用VERIOLG-Introduction to learning verilog code, ensure that you will use VERIOLG a look
dds
- dds产生文件源程序，很好用,调用IP核，在ISE中可以使用-dds files generated source code, useful, called IP cores, can be used in the ISE
lcd1602
- 基于FPGA的lcd1602的vhdl程序设计-design of lcd1602 based on fpga in the lunguary of vhdl
uart
- 一个功能很强大的异步串口例子，用vhdl完成，波特率等参数可以调整。-A feature very powerful example of asynchronous serial interface, complete with vhdl, baud rate parameters can be adjusted.
VHDLlearn
- 一个介绍vhdl语言的PPT文档，可以快速上手学习vhdl语言。个人觉得初学者可以-A descr iption language vhdl PPT document, you can quickly get started learning vhdl language. Personally feel that beginners can see
PN7_gen_wtb
- 一个用vhdl语言写的产生伪随机数PN7例子，经过altera的fpga测试可以使用。-Written in a language with vhdl generate pseudo-random number PN7 example, after the fpga altera test can be used.
statemachine
- 一个用vhdl语言写的交通灯控制的例子，可以很好的学习vhdl语言中状态机的使用。-Written in a language with vhdl traffic light control case study can be a good vhdl state machine language to use.
vspi
- 一个用vhdl语言写的spi接口实例，经过altera的fpga测试可以使用。-Written in a language with vhdl spi interface to an instance, after the fpga altera test can be used.
key44
- 4x4鍵盤使用語法為VHDL，基於cyclone-4 x 4 keyboard using VHDL
traffic_control
- verilog语言实现的交通灯控制程序，能同时对两个方向的交通进行控制-it is a traffic control program that control two way traffic, written in verilog language
multiplier
- This file implemented a multiplier in VHDL