资源列表
lcd_vhdl
- 这是液晶的VHDL版写的驱动程序，能够控制1602液晶的显示-This is the LCD diver code that is written by vhdl
ad0809
- 本程序基于ad0809，通过数码管显示0V--+5V电压。-The program is based on ad0809, via digital display 0V-+5 V voltage.
adder
- 8 BIT STRUCTURAL CODE IN VHDL
booth
- BOOTH MULTIPLIER IN VHDL
Counter_Design_Block
- Here is a code for a simple counter based on verilog
square
- This a verilog code for the generation of a square wave-This is a verilog code for the generation of a square wave..
Decoder
- This a basic code for the decoder based on verilog.-This is a basic code for the decoder based on verilog.
bcd_to_binary
- bcd to binary verilog
sine_vhdl
- this a snipet of code about the sine generator implementation in vhdl-this is a snipet of code about the sine generator implementation in vhdl
m_vhdl
- 设计一个伪随机序列发生器，采用的生成多项式为1+X^3+X^7。要求具有一个RESET端和两个控制端来调整寄存器初值（程序中设定好四种非零初值可选）。-Design a pseudo-random sequence generator, using the generating polynomial 1+ X ^ 3+ X ^ 7. Requires a RESET terminal end and two control registers to adjust the initial valu
series_port
- 用verilog语言编写的串口收发程序，可以进行429总线数据与rs232口的通信。-With verilog program written in serial transceivers, can be 429 bus data and rs232 mouth communication.
verilog_EXAMPLE
- verilog编写的例程指导，包括入门教程和一些设计实例-verilog routines written guidance, including the Getting Started tutorials, and some design examples