资源列表
ch5
- VHDL技术基础；第五章；介绍VHDL的进阶学习；介绍数据对象、设计实例、继续语法的学习；-technology of vhdl；u5
ch6
- VHDL技术基础；第六章；介绍VHDL的宏功能模块以及ip核应用-technology of vhdl；u6
loop_with_mac
- 88e1111配置以及fpga的mac模块的配置文件-configuration of 88e1111 and mac ip
key_smiao
- vhdl语言编写的矩阵键盘采集程序，调试通过-the matrix keyboard VHDL language acquisition program, debug through
SDRAM
- 用XilinxSC1500控制SDRAM的一段VHDL代码。控制SDRAM每个时钟内输出地址所在的一个数据。-For some VHDL code with XilinxSC1500 Control SDRAM. Control SDRAM Each clock output address where a data.
hyalite3
- 数字钟1、具有时、分、秒计数显示功能，以二十四小时循环计时。 2、具有清零，调节小时，分钟的功能。 3、具有整点报时同时LED灯花样显示的功能。 -Digital clock 1, with hours, minutes, seconds count display features cyclic timing twenty-four hours. 2, has cleared, adjust the hours, minutes function. 3, with the patt
hyalite4
- 四位拨码开关提供8421BCD码，经译码电路后成为8段数码管的字形显示驱动信号a,b,c,d,e,f,g。-The four DIP the switch provides 8421BCD yards after decoding circuit 8 digital tube-shaped display drive signal a, b, c, d, e, f, g.
hyalite5
- 设计一个四舍五入判别电路，其输入为8421BCD码，要求当输入大于或等于５时，判别电路输出为１，反之为０-Design a rounding discriminating circuit, its input 8421BCD code required when the input is greater than or equal to 5, the output of the discriminating circuit 1, and 0 otherwise
adaptive_lms_equalizer_latest.tar
- It is the code for Adaptive Equalizer LMS Algorithm-It is the code for Adaptive Equalizer LMS Algorithm..!!
src_adc
- AD采集与DDC、FIRD等滤波vhdl程序，adc为lvds接口-The AD acquisition, DDC, FIRD etc. filtering procedures, adc lvds interface
shr_spi3.tar
- cadence环境下的spi3接口实现，包含源代码和仿真文件-SPI3 interface under cadence， include the source file and the simulation file
Dny_LCD
- LCD verilog codes for labrotuary