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  1. miaobiao

    0下载:
  2. 用VHDL语言实现对FPGA的程序编写,实现秒表功能。-Using VHDL FPGA program written stopwatch function.
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-11-25
    • 文件大小:363.79kb
    • 提供者:秦丽媛
  1. jiafaqi

    0下载:
  2. 用VHDL语言实现对FPGA的程序编写,实现加法器功能。-FPGA program written using VHDL adder function.
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-12-03
    • 文件大小:218.37kb
    • 提供者:秦丽媛
  1. liushuideng

    0下载:
  2. 应用VHDL语言实现FPGA的编程,实现流水灯功能。-Application VHDL language for FPGA programming, light water feature.
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-11-26
    • 文件大小:234.97kb
    • 提供者:秦丽媛
  1. anjianshumaguan

    0下载:
  2. 应用VHDL语言实现对FPGA的程序编写,实现按键数码管的功能。-Using VHDL language to write FPGA procedures to achieve the key function of the digital tube.
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-12-02
    • 文件大小:88.45kb
    • 提供者:秦丽媛
  1. assg-9-1-(lift-controller)

    0下载:
  2. Lift Controller in vhdl using process statement and state disgram
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-11-01
    • 文件大小:19.82kb
    • 提供者:Milind
  1. assg-9-2-(trafic-light-controller)

    0下载:
  2. Traffic light Controller in vhdl using process statement and state disgram
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-11-22
    • 文件大小:110.59kb
    • 提供者:Milind
  1. ethernet_10ge_mac_latest.tar

    0下载:
  2. The 10GE MAC core is designed for easy integration with proprietary custom logic. It features a POS-L3 like interface for the datapath and a Wishbone compliant interface for management. The core was intentionally designed with a limited feature se
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-11-25
    • 文件大小:905.14kb
    • 提供者:ke
  1. sockit_owm_latest.tar

    0下载:
  2. 1-wire master written in Verilog HDL, ready for integration into a FPGA or ASIC based SoC. A port of the 1-wire Public Domain Kit (version 3.10r2) from Maxim is also provided, with all the code required for integration into the Altera development
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-11-21
    • 文件大小:536.35kb
    • 提供者:ke
  1. Elliptic_Curve_Group_latest.tar

    0下载:
  2. 椭圆曲线群的核心是计算在椭圆曲线群的两个元素的加入,并在椭圆曲线组相同的元素的加入。-The Elliptic Curve Group core is for computing the addition of two elements in the elliptic curve group, and the addition of identical elements in the elliptic curve group.
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-11-24
    • 文件大小:567.48kb
    • 提供者:ke
  1. Tate_Bilinear_Pairing_latest.tar

    0下载:
  2. The Tate Bilinear Pairing core is for calculating Tate bilinear pairing especially on super-singular elliptic curve in affine coordinates defined over a Galois field , whose irreducible polynomial is . (For improving security, an irreducible po
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-11-11
    • 文件大小:482.47kb
    • 提供者:ke
  1. tiny_tate_bilinear_pairing_latest.tar

    0下载:
  2. Tiny Tate Bilinear Pairing core is for calculating a special type of Tate bilinear pairing called reduced pairing.-Tiny Tate Bilinear Pairing core is for calculating a special type of Tate bilinear pairing called reduced pairing.
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-11-29
    • 文件大小:1.07mb
    • 提供者:ke
  1. openmsp430_latest.tar

    0下载:
  2. The openMSP430 is a 16-bit microcontroller core compatible with TI s MSP430 family (note that the extended version of the architecture, the MSP430X, isn t supported by this IP). It is based on a Von Neumann architecture, with a single address s
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-11-10
    • 文件大小:36.25mb
    • 提供者:ke
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