资源列表
VHDL
- VHDL的4bit*4bit的有符号无符号的乘法除法实现-VHDL unsigned signed to achieve the multiplication division
ddc_5247
- its a ddc cerilog file
Arbitrary-waveform-generator
- 任意波形信号发生器 利用FPGA器件产生控制信号及数据信号，经DAC0832和TL082转换产生波形 -Arbitrary waveform generator control signals generated by FPGA devices and data signals generated by the waveform converter DAC0832 and TL082
ECC in VHDL
- ECC Cryptography in VHDL . Very Helpful for showing
ADC0809-control-module-code-of-VHDL
- 此为基于FPGA的直流电动机伺服系统的设计，具体为ADC0809控制模块的VHDL代码-This is based on FPGA for dc servo system of the design, concrete for ADC0809 control module code of VHDL
Law-20-80
- 20-80定律，一个复合设计，同样符合很多方面的管理定律。-20-80 law, a composite design, also in line with the management of many aspects of the law.
cont60
- 六十进制加法器 可以实现六十位的技术功能-Six decimal adder can achieve the technical features sixty
uart_verilog
- uart串行口,用Verilog编写的.供大家参考-uart serial port, using Verilog prepared. For your reference
upcounder_verilog
- the up counter are designed to the case statement to perform the counter operation in verilog.
verilog-lfsr-updown-counter
- Verilog 8 bit LFSR Up-Down Counter
AD1674-control-module-code-of-VHDL
- 此为基于FPGA的直流伺服系统的设计，具体为AD1674控制模块的VHDL代码-This is the dc servo system based on FPGA design, specific for AD1674 control module code of VHDL
experience
- 一位行业精英总结的自己25年的嵌入式从业经验，读后启发十分大，建议大家详读一下-A very professional person s summary of his 25 years experience in this area . worth reading