资源列表
a-VHDL-completed-8-of-16-significant-median-band-
- a VHDL completed 8 of 16 significant median band of frequency meter
uart_verilog
- UART串口通信代码，FPGA编程，用Verilog代码编写-UART serial communication code, FPGA programming with Verilog coding
exp_cpu
- CPU代码-VHDL语言，实现了CPU的基本功能。-CPU code-VHDL language, the realization of the basic functions of the CPU.
chap9
- 本程序是关于学习VERILOG语言的案例，方便读者快速掌握VERILOG语言的基本语法，操作等-This program is about learning the language of the case VERILOG to allow readers to quickly master the basic syntax of the language VERILOG, operation, etc.
mouse_control
- 1、 用FPGA实现PS/2鼠标接口。 2、 鼠标左键按下时十字形鼠标图象的中间方块改变颜色，右按下时箭头改变颜色。 3、 Reset按键：总复位。 -one with FPGA PS / 2 mouse interface. 2, the left mouse button pressed cruciform images in the middle mouse to change the color box, press the right arrow at the change
filter_ex1
- DSP builder 模块搭建的fir -DSP builder module built fir
manchesterbyxilinx
- 曼彻斯特编解码的实现（Verilog）,包含有测试文件。-manchester encode and decode with verilog，Test File is included。
I2C_master_code
- 主要介绍，I2C总线主设备发送数据给从设备，代码实现是用Verilog语言实现的，对硬件设计者有很大好处-Introduces, I2C bus master to send data to the slave device, code is implemented in Verilog language, the hardware designer of great benefit
ECC
- Hardware Implementation for Tripling Oriented EC -Hardware Implementation for Tripling Oriented EC
sing
- VHDL实现唱歌的功能，非常好就对了~ -VHDL functionality to achieve a good singer, very good on the ~
Graphic_LCD
- Monochrome Display driver
add_rounding
- 一个基于Matlab+Simulink的带Rounding功能的加法器实现