资源列表
Encoder_Using_Assign_Statement
- Encoder Using Assign Statements: Unlike a multiplexer that selects one individual data input line and then sends that data to a single output line or switch, an Encoder takes all the data inputs one at a time and converts them to a single encoded o
gal
- 使用native图形引擎的数据结构和fb(Framebuffer)的驱动程序
adc7663
- 介绍了ad7663的转换程序的VHDL描述-Introduced ad7663 VHDL descr iption of the conversion process
6.5inch-LCD-demo
- verilog 驱动LCD显示，带自动循环功能。for driving 6.5inch LCD.
ALU
- VHDL code for 3 bit ALU
usb_phy
- umti协议中的usb1.1的verilog原文件，可公实现usb2.0做参考-umti the agreement usb1.1 verilog the original documents, the public can refer to achieve usb2.0
BCDMULTIPLIER
- BCD MULTIPLIER PROGRAM
cpu
- verilog 8 bit cpu working condition but need minor modification
rmfilter
- 低通滤波器在QUARTUS7.0开发环境下的文本与框图结合的实现方法的源代码-Low-pass filter QUARTUS7.0 development environment in the text and diagram combination of methods to achieve source code
曼彻斯特编解码器设计
- Verilog的曼彻斯特编解码
manchester_verilog
- 采用Verilog HDL语言编写的曼彻斯特码， 文件列表： help md.v md_tf.v me.v me_tf.v med.v-Using Verilog HDL language of the Manchester code, the file list: helpmd.vmd_tf.vme.vme_tf.vmed.v
csa_32
- The folder gives the 32 bit carry adder chain. IN CSA for cin = 1 or 0 ripple carry adders are used.-The folder gives the 32 bit carry adder chain. IN CSA for cin = 1 or 0 ripple carry adders are used.