资源列表
I2C_Single_Master
- I2C Single master written in Verilog Libero Designer core generator.-I2C Single master written in Verilog Libero Designer core generator.
module-10_verilog
- Descirbe about PHS module time
learning-about-FPGA
- 夏宇闻老师谈学习Verilog的经验，很有参考价值啊-XIA Wen Verilog learning about the experience of the teacher, a good reference ah
dlx
- 一个简单的流水线cpu程序，具有加减乘除，移位等功能。-a simple stream
zorro_to_wishbone_bridge_latest.tar
- This project intends to create a bridge between Wishbone and the Amiga Zorro II and Zorro III busses. As in the Amiga 3000/4000 computer families, it is intended to support both the Zorro II and Zorro III protocols at the same time on the same bus.
full_adder
- 4 bits architecture full adder
12进制计数器
- 应用VHDL语言编写十二进制计数器
shierjinzhi
- 十二进制计数器应用VHDL源代码编写的，程序易懂-Ten binary counter applications written in VHDL source code, the program easy to understand
VGA
- 基于EPM240的VGA接口实验，在电脑显示屏上实现了两个框-Based on the EPM240 the VGA interface experiment, two boxes on the computer screen
bcd_adder
- verilog code for bcd adder
waveform-generator-o-VHDL-program
- 实现4种常见波形正弦、三角、锯齿、方波（A、B）的频率、幅度可控输出（方波 --A的占空比也是可控的），可以存储任意波形特征数据并能重现该波形，还可完成 --各种波形的线形叠加输出。 -Achieve the four kinds of common sine wave, triangle, sawtooth, square wave (A, B) the frequency and amplitude controlled output (square wave- A dut
LM3SUARTSENDFIFO
- LM3S系列UART例程：发送FIFO触发中断原理-LM3S Series UART routines: Send principle of FIFO trigger interrupt