资源列表
spi_master_slave
- 同步串行数据传输SPI的源代码，它可配置成主机或者从机，挂在总线上。-Synchronous serial data transmission the SPI--s source code, it can be configured as host or slave, hanging on a bus.
DES
- 在ISE平台上，利用Verilog编程实现数据的DES加密-In the ISE platform, using Verilog programming DES data encryption
timeclk
- 数字时钟数码管显示时分秒，每一个小时蜂鸣器响2秒，课程设计，验证通过-Digital clock digital display minutes and seconds, every hour the buzzer 2 seconds, curriculum design, verification by
Wave_Generater
- 采用CycloneII做的多种波形发生器&频率计。有源码和仿真图，工具是QuarteusII。-CycloneII done using a variety of waveform generators & frequency meter. There is source code and simulation diagrams, tools QuarteusII.
STOPWATCH
- 是基于FPGA/CPLD的跑表程序，可以存储记录多个运动员的跑步时间，是利用VHDL语言编写的，可以有助于学习EDA技术，可以参考学习，可以帮助你完成VHDL语言的课程设计。-Is based on FPGA/CPLD s stopwatch program, many athletes can store records of running time, is the use of VHDL language, and can help to learn EDA, can refer to t
SCX4x21_V1.19_rom
- Firmware for samsung scx4521F
jtd
- 实现十字路*通灯控制 以及数码管显示 4个交通灯 以上板验证-Crossroads traffic light control and digital display four traffic lights above board verification
DDRCHv11
- Source code for ddr2 dram controller for BEEE
uartfifo
- 一个基于verilog的fifo的例子，由数据产生模块产生数据传到fifo中，然后同过发送模块将数据发到上位机上。-One based on the fifo verilog example, by the data generation module generates data to the fifo, and then sent over the same module sends data to the host computer.
umi-uta-1273
- thesis on video codec on fpga
seccount
- 用VHDL语言设计电子数字秒表。包含相关文件及说明，用户可以在Xilinx ISE 环境下运行。-With VHDL language design digital stopwatch. Contains the corresponding code and all documents. Users can Xilinx ISE environment in operation
DAC-verilog
- dac数模转换程序，实现16bit数据转换功能，希望能帮到大家，互相学习-DAC digital analog conversion process, the realization of 16bit data transformation function, hope to help you, to learn each other