资源列表
x3cs400_uart
- 基于X3cS400的串口通讯程序，开发环境ISE7.0，使用verilog编写。可以使用串口调试助手在pc机上查看字符。-UART communication program based on X3CS400 FPGA， develop enviroment： ISE7.0，completed by verilog。 The result could be seen on the Uart debug assitant.
AD
- 基于ADC0809的数据采集系统，对0~5V电压采集，显示到数码管显示-ADC0809 based data acquisition system, for 0 ~ 5V voltage of the collection, display to the digital tube display
crc_ccit_8
- crc_ccit, 数据位宽为8，verilog编码-crc_ccit, datawidth is 8,coding by verilog
crc32_8
- crc32,数据位宽为8，verilog编码-crc32，datawidth is8,coding by verilog
crc16_8
- crc16,数据位宽为8，verilog编码-crc16 ,datawidth is 8,coding by verilog
crc12_4
- 数据位宽为4，crc12，verilog编写-crc12 datawidth is 4，coding by verilog
crc8_4
- crc8代码 数据位宽为4 ，用verilog编的码-crc8 datawidth 4 verilog
SIGNAL_GEN
- 利用EDA的VHDL硬件描述语言设计的函数信号发生器，可以产生递增、递减斜波，三角波，阶梯波，正弦波，方波-The use of EDA, VHDL hardware descr iption language design function of the signal generator can generate increased progressively decreasing ramp, triangle wave, step-wave, sine wave, square wave
CANProtocolControllerIPCoreinVerilog
- 一种基于CAN协议的IP核源代码，用Verilog语言实现-CAN Protocol Controller IP Core in Verilog.
clock
- 秒表的verilog语言实现，个人课程设计代码，已验证！实现显示秒，分，时暂停，修正等功能。-Stopwatch' s verilog language implementation, personal curriculum design, code, and has been verified! Implementation show seconds, minutes, suspended, amendment and other functions.
riscfile
- 本程序主要介绍了risc处理器的基本功能单元的程序，以及文档说明，希望对大家有用-This program focuses on a risc processor, the basic functional unit of the procedures and documentation and hope for all of us
Microprogramcontroller
- 微程序控制器部件实验，使用VHDL语言使用Quartus测试通过，模拟CPU-Micro-program controller component experiments, the use of VHDL language use Quartus test, simulation CPU