资源列表
ALU.vhd
- Desarrollo de la Unidad Légica Aritmética (ALU) en VHDL
ROM
- ROM在FPGA内的实现方法，简单的例程-ROM
RAM_DDS
- 使用硬件描述语言，在FPGA中实现直接数字频率合成-Use of hardware descr iption language, in the FPGA to implement direct digital frequency synthesis
EDAVHDL
- VHDL硬件描述语言 MAX+PLUSⅡ介绍 CPLD数字发展实验系统简介以及十个数字电路和数字系统实验的源代码和介绍-VHDL hardware descr iption language introduced the MAX+ PLUS Ⅱ Introduction CPLD digital development of experimental systems, as well as 10 digital circuits and digital systems, the source c
BCD
- BCD\七段显示译码器 数码管段显示发光二级管是共阴连结，所以显示高电平有效，即哪一段的驱动信号为高电平，则对应段发亮-BCD \ seven-segment display decoder digital tube sections show light-emitting diode is a link to a total of yin, it showed high and effective, that is what section of the drive signal is h
RAM
- this code is for the ram blocks and it is very essential if you are going to implement asic
OFDM
- this code is for orthogonal frequency devision multiplexing and it is essential for the communication blocks-this code is for orthogonal frequency devision multiplexing and it is essential for the communication blocks
SIPO
- this code is designed to perform serial to parallel it is essential to every design
PISO
- this code is designed to perform parallel to serial operation it is very essential in every design
multi-functional_digital_clock
- 基于verilog的多功能数字钟，内含各功能模块-Verilog-based multi-functional digital clock that contains the function module
27_examples
- FPGA很有价值的27例，VHDL编写，望对大家有所帮助哦！-FPGA valuable 27 cases, VHDL writing, hope you all have a right to help Oh!