- OFDM This program used to simulate the ofdm system in AWGN and fading channel with specified parameters given in the code.
- Multi-seven-segment combine 5 seven segment at a time
- WorkerThread Simple utility class used only to mark methods that are not executed on the UI thread (or Event Dispatch Thread in Swing AWT.) This annotation s sole purpose is to help reading the source code. It has no additional effect.
- Ch design of cache to remove tag bits
- IC 基于片上系统的炒茶机控制器程序代码
资源列表
tlc2543AND11channel
- 11路串行AD采集芯片TLC2543，12BIT精度输出，100Khz，采用VERILOG HDL编写，占用200个LE-11-Channel Serial AD acquisition chip TLC2543, 12BIT accuracy of the output, 100Khz, using VERILOG HDL preparation, taking up 200 LE
ds18b20s4
- 四路DS18B20的verilog HDL 代码，精度为1℃无须转换数据，根据输入地址改变直接输出结果。占用600个LE资源，相对于单路程序，更为精减-Four DS18B20 the verilog HDL code, and an accuracy of 1 ℃ without converting the data, enter the address change in accordance with the direct output. Occupy 600 LE resources,
dac121
- 采用verilog编写的高速串型DA芯片dac121驱动代码，占用le较少，效率高，目前我应用在较多产品上-Verilog prepared using high-speed string-type DA-chip dac121 driver code, occupation le small, high efficiency, the current I applied to more products
ADC124
- 采用verilog编写的高速串型AD采集芯片adc124驱动代码，占用le较少，效率高，目前我应用在较多产品上-Verilog prepared using high-speed string-type AD Acquisition chip adc124 driver code, occupation le small, high efficiency, the current I applied to more products
counter
- Ring Counter implemented in VHDL usign finite state machine design.
latch
- Latch VDHL by xilinx
flipflop
- FlipFlop VDHL by xilinx
TLC5510
- VHDL实现对TLC5510的控制，带有signaltap仿真图-VHDL implementation of the TLC5510 control, with signaltap simulation diagram
BCD_sevenseg
- BCD seven segment by xilinx
traffic
- Light traffic by xilinx
Full_Adder
- Full Adder for Xilinx