资源列表
lcd1602andveilog
- 非常好的程序，大家可以下载来学习-Very good program, you can download to learn ~~~~~~~~~~~~~
SW_HEX
- SW_HEX.rar是verilog编写的按键计数功能源代码-SW_HEX.rar is written in verilog achieve counting function keys
dds_last
- 用VHDL编写的DDS，实用简洁，利于学习交流-Prepared using VHDL DDS, practical simplicity, conducive to learning exchange
traffic_light
- this project is traffic lights on fpga. ı used xilinx ise and simulated modelsim. [used spartan 3e development kit]. -this project is traffic lights on fpga. ı used xilinx ise and simulated modelsim. [used spartan 3e development kit].
vhdl-beginner
- 很好的VHDL初学者资料，很好的VHDL初学者资料-Good information for beginners VHDL, VHDL good information for beginners
cpld_ads7844_50M(9-24)
- 用ads7844采集数据，用cpld做时序控制，通过串口观察和记录采集结果，用verilog编写，通过开发板验证-Collected data using ads7844 timing control with cpld verilog prepared by the serial observe and record collection results through the development board verification
chapter_listing
- Embedded SoPC Design with Nios II Processor and Verilog Examples
myUART
- 这是我用Xilinx公司的sparten3开发板,ISE集成开发环境，用VHDL语言开发的串口全双工通信程序，供大家参考，共同学习。-This is the company I used the sparten3 Xilinx development boards, ISE Integrated Development Environment, Using VHDL development of the full-duplex serial communication program, for
aa
- 簡易的七段猜數字，先設定所猜數字後，按下a鍵輸入，開始猜數字，每輸入兩數字後，按下a鍵確認，更新上下限。-Simple seven-segment number guessing, first set the number guessing, and then press a key to enter the start number guessing, each of the two digital input, press a button to confirm, update the up
vhdl-beginner
- VHDL入门，适用于VHDL初学者。结合MaxplusII开发环境，给出了一些例子。
altera_modelsim6.1g
- altera_modelsim 6.1仿真时常见问题的总结-altera_modelsim 6.1 Simulation summary of the Frequently Asked Questions