资源列表
spi
- SPI的Verilog实现，好用的代码。-SPI Verilog implementation, good code.
timer
- 能够实现小时（24进制）、分钟和秒钟（60进制）的计数功能 具有复位功能 功能扩展：具有整点报时提示、定时闹钟等功能 -To achieve an hour (24 hexadecimal), minutes and seconds (60 hexadecimal) count function function reset function expansion: with the whole point timekeeping tips, regular features such
Verilog
- 这是 夏宇闻Verilog数字系统设计教程中部分例程代码，适合初学Verilog的人-This is Xia Yu smell Verilog digital system design tutorial part of the routine code, suitable for beginners of Verilog
Lattice-Machxo-FPGA-Loader
- Application note (source code + documentation) about how to use an FPGA (Lattice Machxo) to perform a ISP programming of a parallel flash.-Application note (source code+ documentation) about how to use an FPGA (Lattice Machxo) to perform a ISP progra
Serial
- VHDL语言的串行通讯程序，已调试过了可以下载使用-VHDL language serial communication program, you can download have been used to debug
LCD1602_Verilog
- lcd1602的verilog语言程序，对学习fpga有帮助，简单易上手！-lcd1602 the verilog language program, to learn fpga help, simple approachable!
FPGA-Channel-segmentation-design
- Channel segmentation design for symmetrical FPGAs.
shouhuoji
- 用Verilog语言实现自动售货机，外加实现课件-Automatic vending machines with the Verilog language, along with realization of courseware
8051参考设计_Oregano System 提供_vhdl
- 8051参考设计，与其他8051的免费IP相比，文档相对较全，Oregano System 提供-8051 reference design, and other free IP in 8051 compared to relatively entire document, Oregano System for
DSP48E1_ComplexMul
- This module does Complex multiplication based on Xilinx DSP48E1 dsp block. Proved on xilinx Virtex 6 Devices
lift_controler-verilog
- 电梯控制程序！！ verilog 描述的-Elevator control procedures! ! described in verilog
final_7
- 7. 對於按鍵輸入密碼鎖，假設reset後，七節燈管顯示「0」，而且使用sw5、sw6二個，那麼只要sw5按下且放開後，七節燈管就顯示「5」，而只要sw6按下且放開時，七節燈管就更正顯示值「6」。-7. For the key to enter a password lock, assuming that reset after the seven lamp displays " 0" , and the use of sw5, sw6 2, then press and rel