资源列表
dCACHE
- Vhdl写的数据cache,根据Verilog程序改编-Vhdl write data cache
trafficlight
- 一个简单的交通灯的verilog语言的描述，对于新手来说较为适合学习-this is a easy VHDL code for a newer in learning VHDL,it supply with a simple code that describes traffic light
MUX
- VHDL code for MUltiplexer
ahb_ebc
- Sipmle external bus controller realization on Verilog HDL with AHB interface. Support RAM/ROM/NAND Flash devices.
Dm9000a_Verilog
- 本文为实现高速数据的实时远程传输处理,提出了采用FPGA直接控制DM9000A进行以太网数据收发的设计思路，实现了一种低成本、低功耗和高速率的网络传输功能，最高传输速率可达100Mbps。-DM9000 driver
mt48lc2m32b2
- SDRAM控制核，已经经过测试，完全可以稍加修改后应用-SDRAM control nuclear, has been tested, we can use a slightly modified
嵌入式系统试验报告-乘法器-VHDL语言
- 嵌入式系统的乘法器试验报告 包括源代码 用VHDl语言编写-Embedded System multiplier test report including source code language used VHDl
daima
- 适用于xilinx的CPLD产品，曼彻斯特编码-Decoder for Xilinx CPLDs Customer Pack
uart_ip
- UART硬件描述语言代码，经过验证可用，符合spec协议-UART hardware descr iption language code, proven available, in line with the protocol spec
encoder823.v
- An encoder is a device, circuit, transducer, software program, algorithm or person that converts information one format or code to another, for the purposes of standardization, speed or compressions.-An encoder is a device, circuit, transducer, softw
cordic_1-0
- Cordic算法的另一种C++实现，只是一个样本，可以用TubroC，等来查看-Cordic algorithms to achieve another C is a sample that can be used TubroC, etc. to see
VERILOGBLOCK
- 在blocking 模块中按如下写法，仿真与综合的结果会有什么样的变化？作出仿真 波形，分析综合结果。 -in blocking module by the following wording, simulation and synthesis of the results will be what kind of changes? Make simulation waveform analysis and comprehensive results.