资源列表
24
- 2-4解码器的vhdl描述，行为域的描述，-24 decode
mancheester_v
- 用Verilog HDL实现的曼彻斯特编码器和解码器。
diwu
- 应用VHDL语言编写设计一个正负脉宽可控的4分频的分频器。程序简单易懂；-Application of VHDL language to design a controlled positive and negative pulse frequency divider 4. Procedures are simple and easy to understand
alu_simulation
- VHDL alu unit design and simulation with RAM, ROM, clock generator and 2 simple programs to execute.
di
- 应用VHDL语言编写设计一个正负脉宽可控的4分频的分频器。程序简单易懂；-Application of VHDL language to design a controlled positive and negative pulse frequency divider 4. Procedures are simple and easy to understand
Verilog--Digital-Clock
- A digital Clock Implemented on Spartan-3, coded in Verilog... bit and ucf files have been attached along-with the source v-file- Will help a lot the students, beginners and hobbyists.
System-Bus
- Design of System Bus
code
- 某数据传输系统，试图利用300-3400Hz的话音通 道进行载波传输，波形信道为加性高斯白噪声信道。 –采用线性传输，收发两端拟采用滚降系数0.5的根 号升余弦滤波，以解决采样点失真问题。 –以下仿真采用无记忆采样信道模型，其中受器件限 制，复基带采样点平均功率受限为1，复基带采样 点噪声功率为可调参量-A data transmission system, trying to use 300-3400Hz voice channel for carrier transmission, wave
vhdl2---Copy
- THIS THE BEST PROGRAM IN VHDL LANGUAGE-THIS IS THE BEST PROGRAM IN VHDL LANGUAGE
Finite-State-Machines
- 此壓縮檔包含四個資料夾(1)Moore Machine(2)Mealy Machine(3)Memory(4)A mini system，學習如何以階層化的方法去撰寫系統內部的小工作區塊，並了解迷你CPU內部的記憶體簡單的運作情形&資料串流-design the finite state machine and the mini system.
ProjectLoto
- VHDL Project for a loto application
scaler
- VHDL描述的简易图像缩小模块，将PAL制720×576的图片缩小为512×410，采用最近临域法，13.5MHz时钟下可实时处理PAL视频。