资源列表
uart_verilog
- 包含UART口的VERILOG源程序，该程序在FPGA上验证通过，可作为芯片设计，或FPGA设计的一个完整IP核，硬件设计的兄弟们可参考一下。-include UART port of VERILOG source, the program tested in FPGA, as chip design, or FPGA design of a complete IP cores, hardware design brothers can make reference.
Binary_to_BCD_Converter
- This is a binary to BCD convert designed by using the “shift and add-3 algorithm”. The verilog code of basic cell add-3 is also included in this file.
converter
- 多位2-10进制转换与10-2进制转换，用十进制加法器实现-2-10 and 10-2 convert binary number base conversion, decimal adder realization
pingpang
- spartran_3A乒乓球gameboy的设计与开发-a Table tennis game in spartran_3A
HAS160
- HAS-160 Cipher algorithm verilog code
mux
- This file is about mux in ISE by VHDL language.
VHDL语言实现3—8译码器
- 应用VHDL语言编写的3—8译码器，简单易懂
chenxu
- 3—8译码器是由8个3输入“与非”门构成，采用VHDL语言描述，从行为、功能对3—8译码器进行描述，不仅逻辑设计的容易，而且阅读方便。-3-8 decoder input by 8 3 " and not" the door structure, use of VHDL language descr iption, from the behavior and function of the 3-8 decoder is described, not only the logic
src
- IQ correction module in VHDL
samll
- 这是一组Verilog的代码小程序，适合新手练习使用．-This is a group of small Verilog code procedures for the use of novice practitioners.
FIR5
- 5阶数字滤波器FIR5，包括了Textio模拟等完整设计，VHDL-5_level digital filler, including Textio simulation
123
- 设计一个输入为48MHZ，有四个输出端分别为1HZ，10HZ和100HZ，1KHZ的分频器-hello word