资源列表
VHDL
- 基于EMP 7128的数字式相位测量仪相位测量仪
Feedback-control-module-VHDL-code
- 此为基于FPGA的直流伺服系统的设计，具体为反馈控制模块的VHDL代码-This is the dc servo system based on FPGA design, specific for feedback control module VHDL code
verilog-generate
- 很实用的verilog中generate语句使用方法整理 -Useful in verilog generate statements use method
fpga
- 学习FPGA必看文章，相当有价值的，在此隆重推荐哦！-Learning FPGA must see the article, very valuable, highly recommended in this Oh!
uart_verilog
- 串口标准通讯，带奇偶校验和通讯超时故障，带测试文件-The serial standard communication with test files
S9_PS2_LCD
- 1、ps/2键盘输入，通过led显示ascii码 2、稍等1s可以在lcd上显示输入的字符 3、其中键盘上的backspce键是用来清屏的 4、当lcd上显示满字符时，在按下按键自动清屏，从第一行显示。-1, ps/2 keyboard input, through the led display ascii code 2, wait for 1s in the input character lcd display 3, in which key on the keyboard i
fenpin
- 输出比设定的时钟频率小8倍的时钟，实现分频功能，可用于芯片控制。-Output than the set of 8 times the clock frequency of the clock, to achieve frequency division function, can be used for chip control.
61i_async_fifo_v5_1_vhdl
- VHDL Code for FIFO+coregen v5.0
sale-machine-
- 一个FPGA的自动售货机程序，状态机部分很详细，值得参考-A vending machine program the FPGA, the state machine part of the very detailed and valuable reference
my-scaler
- 图像缩放源代码，该代码支持输入bmp文件格式，输出bmp格式。-Image scaling source code, which support the input bmp file format, the output bmp format.
TestFixture
- I2C 控制器的 Verilog测试源程序-I2C controller Verilog source test
VHDL
- 实现4种常见波形正弦、三角、锯齿、方波（A、B）的频率、幅度可控输出（方波 A的占空比也是可控的），可以存储任意波形特征数据并能重现该波形，还可完成 各种波形的线形叠加输出。