资源列表
Template_Slave
- avalon总线的从端口实例代码，简单，易懂，方便初学者学习。-avalon bus example code from the port, simple, easy to understand, easy for beginners to learn.
Antenova-(Legacy)
- Altium DEsigner Antenova libraries
div
- Quartus下VHDL语言编写的常用分频器（2、4、5、8、10、50、100）等，包含模块图。-Frequency divider in common use under Quartus environment,with module block
lut
- 可参数化配置的CAM模块，仿照xilinx IP core设计而成，使用SRL16E基本单元实现，节省空间-Can be parameterized configurable CAM module, modeled xilinx IP core designed, implemented using the basic unit SRL16E, space-saving
chap10
- 本程序是关于学习VERILOG语言的案例，方便读者快速掌握VERILOG语言的基本语法，操作等-This program is about learning the language of the case VERILOG to allow readers to quickly master the basic syntax of the language VERILOG, operation, etc.
I2C_contrl_LED
- I2C的top文件，是按照标准的I2C协议编写的，已通过调试，放心使用-I2C s top document is written in accordance with standard I2C protocol has been through debugging, ease of use
vhdl2
- vhdl设计实例二：测试向量级波形产生，状态机实例-vhdl Design Example Two: Testing the order of waveform generation, the state machine instance
clk
- Verilog HDL clk 带延迟的时钟，对于处理时钟同步问题有益-Verilog HDL clk
miniuart
- This is a uart source written by VHDL .widely used and compatible with Whibone.
FIFO_counters_VHDL.rar
- FIFO和计数器以及时钟控制，用于程控交换机教学，与DSP和ADDA芯片配合完成程控交换机功能,FIFO and counters and clock control, program-controlled switchboard for teaching, with the DSP and complete ADDA chip with program-controlled switchboard function
Lab1-6
- 计算机组成原理，试验1-6源代码.其中试验目的是设计一个MISP CPU-Computer composition principle, test 1-6 source code which test objective is to design a MISP CPU