资源列表
dm9000a_init
- 在QUARTUS开发环境下的，verilog实现dm9000a的初始化-In QUARTUS development environment, verilog realize dm9000a initialization
ledcpu-YSOK-BF
- NIOSII 内核架构LED示例工程及代码-niossii led code an project
VHDL-key-point-of-study-and-example
- 本人多年工程实践及学习总结得到的VHDL学习及应用关键知识点及工程代码示例-VHDL key point of study and good example
leon2
- leon处理器代码，能正确通过design compiler，quartus的综合。-leon handler code, design compiler, quartus integrated properly adopted.
vga_lcd
- 一个通过VGA协议控制LCD的代码，你可以修改行场的参数值，正确地控制不同规格的LCD-A code via VGA LCD protocol control
i2c
- 一段实现I2C协议的代码，能通过design compiler综合-I2C protocol implementation code section, through design compiler synthesis
FIRfilterverilogHDL
- FIR滤波器的verilog HDL代码示例，以16阶为例-Verilog HDL code for fir filter
emif
- 异步EMIF接口，16bit，FPGA程序。-asynchronous emif，16bit，FPGA program
shuzishizhong
- 基于DE2-115开发板设计的一个数字钟，能进行正常的小时、分、秒计时功能，并分别由开发板上面的数码管显示秒（60s）、分（60min）、小时（24hours）的时间。并具有手动调整时间的功能-DE2-115 board design based on a digital clock, and enables the normal hours, minutes, seconds chronograph function, and were above the development board
AES
- AES的加密解密verilog全部源代码-AES encryption and decryption verilog full source code
jingsai
- 微机原理课程实验应用，竞赛抢答器的设计，文本档-Microcomputer Principle Course Laboratory applications, Contest Responder design, text files
Cordic
- block-matching 3D filtering (BM3D) [2], and low-rank regularization [3], single-image based denoising performance has greatly improved, with image details well recovered when the image is slightly noisy. However, with the increase of noise le