资源列表
alu
- 四级流水ALU，能够完成加减乘除开方以及逻辑运算-4 pipeline ALU，which can add,minus,multiply,divide and rooting operation.What s more,it can do logic operation.
Counter_LIUZHIWEI
- 同步计数器，利用有限状态机完成,能够完成000-999的加计数以及减计数功能-Synchronous counter which using finite state machine and able to complete the 000-999 plus count as well as the count function.
mod15adder_LIUZHIWEI-
- 模15加法器，能够完成7段译码以及设计了控制器来控制LED的输出-Module 15 adder, to complete the 7 segment decoding and the design of the controller to control the output of LED
DDS
- 直接数字频率合成器DDS，电类综合实验课程设计-Direct digital frequency synthesizer
eeprom
- eeprom的verilog程序,经测试程序可用-the program of eeprom in verilog.it is tested that can be used.
Binary_search_algorithm
- fpga implementation of binary search algorithm using verilog code
fast_radix10
- fpga implementation of fast radix 10 multiplier using verilog code
RSFQ_Adder
- fpga implementation of rsfq adder using verilog code
booth_recoding
- fpga implementation of booth recoding algorithm using verilog code
deinterleaver_new
- fpga implementation of wimax deinterleaver address generator using vhdl cod
ov7670-1
- ov7670摄像头FPGA数据采集、显示模块，测试可用-ov7670 camera, verilog code, video capture and display
EXAMPLES-ON-SYSTEM-VERILOG.tar
- THIS FILE CONTAINS AROUND 20 USEFUL EXAMPLES ON SYSTEM VERILOG (MEMORY-ARRAYS,LOGICS,DATATYPES ETC.)-THIS FILE CONTAINS AROUND 20 USEFUL EXAMPLES ON SYSTEM VERILOG (MEMORY-ARRAYS,LOGICS,DATATYPES ETC.)