资源列表
???
- This is timer code using VHDL
1
- 一触即发 好玩的效果，基于quartus平台编写(This is a course work, showing some interesting results, welcome to download the exchange)
uart
- 带有fifo的功能模块，具有发送模块和接收功能模块(The function module with FIFO has transmitting module and receiving function module)
DPSK调制解调VHDL程序
- 用于DPSK的调制解调 包括码型变换及反变换过程(Modulation and demodulation for DPSK, including code type conversion and inverse transformation process)
IEEE Standard for Verilog 2005
- IEEE Standard for Verilog 2005
RAM2048X8
- you can add this code to your project if you need RAM2048X8
hp and lp filter
- hp and lp filter verilog code..
16x 16 vedic mulbit
- vedic 16x16 design and teshbench fully working codes..
reconf. router code xylinx
- design and fpga implementation of Routing algorithm for NOC
fir filter design
- FIR FILTER DESIGN IN VERILOG ON FPGA
qam16 modulator
- QAM16 MODULATOR VERILOG CODE ON FPGA
hola mundo2
- hat the image I was created by convolving a true image with a % point-spread function PSF and possibly by adding noise. The algorithm % is optimal in a sense of least mean square error between the % estimated and the true images