资源列表
qingdaqi
- 实现8路选手抢答，抢答时间调整，回答时间调整，回答倒计时显示灯-Achieve 8 players Responder, answer in time to adjust, time to adjust to answer, the answer countdown indicator
fenpin
- FPGA的一个分频程序，FPGA时钟频率问100MHz，进行100000000分频。-A sub-frequency program FPGA, FPGA clock frequency asked 100MHz, for 100 million frequency.
coeff_rom_1_6
- FIR filter basic verilog code for implementation-FIR filter basic verilog code for implementation
coeff_rom_2_5
- FIR filter basic verilog code for implementation-FIR filter basic verilog code for implementation
RS232
- RS232应用头文件，程序开头声明，使用时初始化即可-RS232 application header file, declare the beginning of the program, you can use when initializing
coeff_rom_0_7
- FIR filter basic verilog code for implementation-FIR filter basic verilog code for implementation
te
- vhdl简单应用验证实例,包含设计以及验证源代码-simple vhdl design verify case
ddr_top
- verilog语言ddr3读写程序，axi总线协议，用于ddr3读写测试-ddr3 read and write
sram64
- 随机存储器VHDL代码，已用quartusII6.0验证，可用，可实现模块-Random access memory VHDL code has been used to verify quartusII6.0 can be used to deliver modules
TEST-BENCH.vhd
- test bench for ddr 1
cunchuguanli
- 模拟请求页式存储管理中硬件的地址转换和缺页中断，并用先进先出调度算法（FIFO）处理缺页中断；-Simulation request page storage management hardware address translation and page fault interrupt and FIFO scheduling algorithms (FIFO) processing a page fault
32bit_add
- 32位进位选择加法器 用四位先行进位加法器扩展成32位二进制加法器-32 carry select adder Used four carry-lookahead adder extended to 32-bit binary adder