资源列表
whole
- ov7620的CPLD采集程序，VHDL语言-ov7620 CPLD acquisition procedures, VHDL
clk
- 程序实现数码管日期显示（按键可控制月日、时分、分秒切换）和LCD显示-Program for digital date display (buttons can control the day, hours, minutes and seconds to switch) and LCD display
clk_div2n
- 这是用VHDL 语言编写的参数可以直接设置的2n倍时钟分频器，在运用时，不需要阅读VHDL源代码，只需要把clk_div2n.vhd加入当前工程便可以直接调用clk_div2n.bsf。-This is the VHDL language parameters can be directly installed 2n times the clock dividers, when exercising not reading VHDL source code, clk_div2n.vhd simp
LCD12864
- 利用FPGA在12864液晶屏上显示汉字。配置IO后可直接使用-Use of FPGA in the 12864 character LCD display. IO configuration can be used directly after
coeff_rom_3_4
- FIR filter basic verilog code for implementation-FIR filter basic verilog code for implementation
AD5542
- DA芯片AD5542的驱动程序，已经完成调试-driver to AD5542
GPS_CODE_CORRELATE
- GPS接收机基带信号处理的相关器处理vhdl程序，已经在工程中得到检验，请放心使用。-Correlator GPS receiver baseband signal processing processing vhdl program has been tested in engineering, ease of use.
read_keypad
- this file is keypad in vhdl code
SERIAL_CONTROLLER
- UART控制，使用三段式编写，非常规范，可以通过编译，仿真-UART transmission, the use of three-step preparation, very standard, you can compile, simulation
bt656
- bt656格式转成bt601与ycbcr 4:2:2格式-the bt656 format converted to the bt601 with the YCbCr 4:2:2 format
immediate_float_divide_module
- 单精度浮点数除法器。用组合逻辑实现。高精度。-Single-precision floating point divider.