资源列表
TEN
- 异步的十进制计数器程序源代码，实现十进制计数-TEN CONTER
led2
- niosii+qsya实现的soc简易流水灯程序，适合初学者，。-Niosii+qsya SOC simple light water lamp program for beginners,.
array-led-display-chinese-characters
- 基于fpga驱动点阵显示汉字，4*4点阵，采用Verilog-array led display chinese characters
LCD12864-display-picture
- 基于LCD12864的FPGA驱动液晶LCD12864显示图片-LCD12864 display picture.rar
verilog-HDL
- 蜂鸣器的FPGA设计，verilog语言，工程文件全-Buzzer FPGA-based design
acservoceshiyi
- 交流伺服测试仪程序，程序用来测试交流伺服的性能-AC servo tester program to test the performance of AC servo
m_xulie
- 这是用verilogHDL写的m序列发生器，简单易用，代码非常易读-It is written verilogHDL m sequence generator, easy to use, the code is very easy to read
AD_TLC549
- 这是用verilogHDL写的AD549的FPGA驱动代码，适用于通常的串行AD芯片-It is written in AD549 verilogHDL the FPGA driver code, applicable to the general serial AD chip
DA_TLC5620
- 这是用verilog写的基于FPGA的TLC5620串行DA的驱动代码，稍加修改后试用于通常的串行DA的驱动-This is a FPGA-based verilog write driver code TLC5620 serial DA, the latter slightly modified the trial in an ordinary serial DA driver
xor4b
- 四为异或门，实现全加器的硬件模块，使用VHDL语言实现，主要适用于初学者实例展示，为初学者提供quartus的实例展示。-4 bits xor gate finished with VHDL language， specifically for greenhands and bachelors who just begin with quartus
aaa
- 24位加法计数器，每一个信号的上升沿将使得计数器加1，实现从0 -1 -2 -3…… -22 - 23的循环计数器。-24 States adding type counter， every rising-edge signal increases the counter, and making sequence 0-1-2-...-22-23 cycled.
esjz
- 60-24 模拟时钟分钟小时计数器。 分钟为60标号的计数器从0-1-2-……58-59 循环往复，完成1个分循环，小时循环计数器加1；小时采用24小时制。-60-24 simulator of a clock, 60 is for minutes, starts 0 increased by 1,and cycle period is 60 once a cycle is finished, the 24 adding-type counter will increase by1 and