资源列表
ILX554B_CPLD
- 用CPLD（EMP240T100C5）产生ILX554B的驱动时序，CCD的驱动时序电路程序。用verilog编写。-Drive timing generator ILX554B with CPLD (EMP240T100C5), CCD drive timing circuit program. Written in verilog.
SOBLE_VGA
- 本设计是通过摄像头OV7670采集图像，然后通过FPGA进行边沿检测算法,最后通过VGA进行显示。-This design is through the camera OV7670 capture images, and then through the FPGA edge detection algorithm, and finally through VGA display.
fenpin
- 通过FPGA设计实现的分频模块，仿真可以通过，适合初学者学习。-Through the FPGA design of frequency divider module, simulation can be passed, for beginners to learn.
FPGA_DSPbuilder
- DSPbuilder可直接在MATLAB中调用，生成可执行的VHDL语言。-DSPbuilder can be directly invoked in MATLAB to generate executable VHDL language.
NIOS
- 介绍nios II的使用方法，即在FPGA中可通过C语言实现一些功能。-The use of II NIOS is introduced, that is, some functions can be realized through C language in FPGA.
FPGA(lvbo)
- 基于FPGA的滤波处理，可实现对信号的筛选。-The filtering of the signal can be realized based on FPGA filtering..
music_keypad
- Using PFGA board to play musical note.-Using PPGA board to play musical note.
filters_FPGA2
- this is vhdl code of median filter
BarrelShifter3
- this is vhdl code of BarrelShifter3
dualpreiortyencoder
- this is vhdl code of dualpreiortyencoder
sign-magnitude-adder
- this is vhdl code of sign-magnitude-adder
FPGA-for-signal
- VHDL非常好的波形发生器资料 -VHDL very good waveform generator Information