资源列表
CPLD_PCIE20140613
- 本CPLD程序是针对PLX8311的PCIE局部总线状态机程序，可以实现基于PCIE X1的数据通讯，在实际项目中应用通过-The CPLD Program for PLX8311 the PCIE local bus state program, can be achieved based PCIE X1 data communication, in the actual project application by
led_shift
- 在xilinx的ISE上写的LED灯移动的verilog程序-a verilog code for led-shifting which writed with ise 14.2
Verilog-language-in-ASIC-design
- Inout bidirectional port programming based on Verilog language in ASIC design
E_watch
- 一款电子表芯片，能够能够显示年月日，星期，并且实现闰年的自动调整。-An electronic table chip that can be able to display the date, day of week, and automatic adjustment for leap year.
BKM
- 设计一个11位巴克码序列峰值检测器，巴克码序列为11’b 11100010010。要求 能够检测巴克码序列峰值； 在存在1bits错误情况下，能够检测巴克码序列峰值。 写出测试仿真程序-Design of a 11 Barker code sequence peak detector, Barker code sequence 11 b 11100010010. Claim Barker code sequence can be detected peak 1bits in
count
- 能实现秒分频的计数器,调用元器件，用VHDL语言编写-To achieve second frequency division counter，Calls components, written in VHDL language
ti_C6474evm_fpga_top
- Project file for VHDL design
adder_32bits
- 采用“进位选择加法”技术设计32位加法器 Verilog语言编写-32 bit adder
cach
- LEON2中cach部分VHDL代码 需要完整的请联系我-LEON2 VHDL code
verilog-code-style-specification
- 企业用verilog代码风格规范 本规范规定了IC设计项目开发过程中VerilogHDL源代码的编写总则、要求及模板文件。-Enterprises with verilog code style guide for the preparation of this specification General IC design project development process VerilogHDL source code, requirements and template files.
Verilog-HDL-Coding
- Motorala推荐的Verilog代码规范。对于VerilogHDL语言编写很有借鉴意义。-Motorala recommended Verilog code specifications. VerilogHDL language is useful for reference.
Tetris_final
- FPGA俄罗斯方块。 -采用VHDL编写，该游戏支持PS2键盘输入，VGA视频输出，游戏可以选择不同难度，同时可以记录显示游戏得分。-FPGA Tetris. - Use of VHDL, the game supports PS2 keyboard input, VGA video output, the game can choose different difficulty, while records show game scores.