资源列表
tb_axi4
- 介绍如何使用vivado来调用和封装IP核，测试AXI4总线的三种功能协议。-It describes how to use vivado to call and package IP core test three functions AXI4 bus protocol.
PULSE_CDC
- Clock Domain Crossing (SLOW-to-FAST OR FAST-to-SLOW). This module transfers pulse IN clock domain to OUT clock -Clock Domain Crossing (SLOW-to-FAST OR FAST-to-SLOW). This module transfers pulse IN clock domain to OUT clock
hostreg_make
- Verilog register creator based on text file input.
CIC_interpolator_wer1
- CIC interpolation filter which DOESNT WORK-CIC interpolation filter which DOESNT WORK!!
FPGAbasedprogramable-PROWER
- 本设计提出了一个基于FPGA的程控稳压电源的方案。通过按键向FPGA输入信号，FPGA得到“十位”和“各位”计数脉冲信号，通过计数器模块计数，内部计数器的信号一路送给外部显示电路来显示当前的电压值，另一路经过D/A转换器（DAC0832）输出模拟量，再经过运算放大器隔离放大，控制输出功率管的基极，随着功率管基极电压的变化而输出不同的电压，同时实现双路输出。实际测试结果表明，本系统具有易调节，高可靠性，操作方便，电压稳定度高，其输出电压采用了数字显示的特点。-This design present
cpld-program
- CCD1208驱动时序，波形符合工作要求-CCD1208 drive timing, waveform meet the job requirements
RISC_CPU
- RISC cpu设计，verilog语言，PIC14位指令集-RISC cpu design, verilog language, PIC14-bit instruction set
DDS
- FPGA,ISE12.2,DDS代码，VHDL语言-FPGA, ISE12.2, DDS the code, VHDL language
emmc_cmd_interface_module
- emmc控制芯片CMD命令线主机接口模块,-emmc control chip CMD command line host interface module
SRAM
- 用memory compiler 生成的 512*8的SRAM，经过测试，可用进行读写-With SRAM memory compiler to generate 512* 8, tested, can read and write
ahb
- 基于AMBA2.0的AHB 总线，包括arbiter，decoder，Muxs2m,Muxm2s-Based AMBA2.0 the AHB bus, including the arbiter, decoder, Muxs2m, Muxm2s
src_vtb
- 用verilog实现的维特比译码电路，可以实现维特比译码-With verilog realize Viterbi decoding circuit, Viterbi decoding can be achieved