资源列表
2048Mb_ddr3
- 美光DDR3存储器模型，用verilog语言编写，通用模型-DDR3 MEMORY
oc_mkjpeg
- Pure hardware JPEG Encoder design. Package includes vhdl source code, test bench, detail design document. Written in VHDL. Verified on Xilinx XC4VLX25. Rncode 320x240 bmp picture in 3ms at 50 quality, 100Mhz clock.-Pure hardware JPEG Encoder design.
love
- 用数码管和LED等来显示心形的LOVE，可以送给女朋友的 哦-LOVE heart-shaped digital control and LED display, can be given to a girlfriend
QUAD-SPI-verilog
- 难得的SPI NOR Flash控制器Verilog源代码，支持四路串行通道！-Rare SPI NOR Flash controller Verilog source code, supports four serial channels!
rrc_filter
- this is a verilog code for root raised cosine filter
Verilog-SRAM
- 用verilog hdl语言编写的fpga与片外sram 的读写控制-With the verilog hdl language fpga sram chip with read and write control
hdlc_latest[1]
- HDLC解码控制，包括CRC校验，可以在一片3400A FPGA上实现8解码-HDLC decoding control, including the CRC check can be realized in a 3400A FPGA 8 decoding
mdio
- cpu与phy通信，让cpu能读写phy芯片，实现通信-cpu communication with phy
SDH_module
- SDH帧同步头的检测，并提取其中的语音信息的模块设计-SDH frame sync detection, and extract audio information module design
spi_write
- 一个简单的 SPI 的 verilog 程序 。 包含两个子模块。-A simple SPI' s verilog program. Contains two sub-modules.
Verilog-for-special-ciucuit-design-
- 华为内部员工学习资料，对于想进华为的朋友会有很大帮助。-The internal staff s learning materials in huawei is more helpfull for someone who want to go to huawei.
8253
- 8253计数器接口电路 intel8253是NMOS工艺制成的可编程计数器/定时器，有几种芯片型号，外形引脚及功能都是兼容的，只是工作的最高计数速率有所差异-8253 counter interface circuit