资源列表
Electronwatch
- This a vhdl programme for realise an electron watch by max-plus II. The function includes time showing and time setting. It may be extended to other functions like alarming clock and so forth.
keyq
- 用FPGA 是先键盘的程序，is good for you
x
- ALU flop Detector110 等源代码-ALU flop Detector110 source code, etc.
Lcd
- microchip LCD display program
7Segment2bcd
- vhdl seven segment to bcd 4 bit
transfer
- 基于CPLD的PWM波形的发生器，编程语言为verilog,开发环境为QuartusII.-The CPLD-based PWM waveform generator, the programming language to verilog, development environment for QuartusII.
pld_encod11
- AHDL增量式光电码盘四倍细分后，自动计数转换成绝对数据-AHDL incremental photoelectric encoder segments four times, the automatic counting data into absolute
USB_LOOP
- 该Verilog程序基于USB芯片68013,FPGA50T,实现了两台电脑之间使用两个68013和一个FPGA50T来通信-Verilog program is based on the USB chip 68013, FPGA50T, realized between two computers using two 68013 and one FPGA50T to communicate
scan
- QuartusII中使用VHDL语言，扫描数码管。-QuartusII using VHDL language, scanning the digital tube.
sy5
- 移位寄存器 LIBRARY IEEE USE IEEE.STD_LOGIC_1164.ALL ENTITY ADCINT IS PORT(D : IN STD_LOGIC_VECTOR(7 DOWNTO 0) --来自0809转换好的8位数据 CLK : IN STD_LOGIC --状态机工作时钟 EOC : IN STD_LOGIC --转换状态指示，低电平表示正在转换 ALE : OUT STD_LOGIC --8个模拟信号通道地址锁存信号 START
ycrcb2rgb.v
- 用verilog编写的最简单的YUV转rgb的代码，请大家参考-yuv2rgb，by verilog
a
- 讲述了如何使用ModelSim与Quartus结合进行时序仿真 -Describes how to use ModelSim for timing simulation combined with the Quartus