资源列表
custom_mul
- vhdl编写的硬件乘法器-prepared by the VHDL hardware multiplier
onchip_memory_0
- 在线仿真调试的存储器代码，可在ISE或quartus下完成调试-Online simulation of the memory debugging code can be accomplished under the ISE or Quartus debugging
seven_segment
- 用veirlog写成的七段显示器 可以把十进制转成七段显示器上面的显示数字-Paragraph written by veirlog display can display the metric system into the above paragraph shows that the number of
arbiter
- VHDL源代码共享,资源多多共享,论坛上多多讨论!
cordic代码
- 流水线方式实现，已在实践中运用
song
- 音乐，梁祝，其中应用VHDL编写的全过程梁祝。-Music, Butterfly Lovers, in which the application of VHDL to prepare the whole process of Butterfly Lovers.
Bubble-Sorter
- 冒泡排序算法的verilog实现，基于FPGA-Verilog implementation of the bubble sort algorithm, based on FPGA
cordic
- 实现cordic算法旋转模式的verilog代码-Verilog code for cordic algorithm rotation mode
main_dct
- verilog code for dct
SHERT
- 滚动输出文字 有限状态机：初始、左移、右移、直通 虚拟位、纯状态机-Scroll through the output text Finite state machines: the initial, left, shift right, straight Virtual spaces, pure state machine
std_logic_unsigned
- VHDL的基本库，讲述基本类型的操作，重载等等，代码很规范-VHDL basic library, describes the basic types of operations, overloading, etc., the code is standardized
Controller(FSM)
- Simple Bridge (ESD book figure 2.14) by Weijun Zhang, 04/2001 RT level design using Controller(FSM) + DataPath- Simple Bridge (ESD book figure 2.14) by Weijun Zhang, 04/2001 RT level design using Controller(FSM) + DataPath