资源列表
ADCTR
- 基于VHDL实现AD7891转换时序的控制器-perfect progranm by vhdl
recovery
- 恢复时钟信号的代码,用于数字通信中，used to recovery the timing from data-used to recovery the timing from data
Adder_Kogge_Stone_32bit_With_Test_Bench
- verilog source code and test bench of Adder Kogge Stone 32-Bit
7_1LVDS_serilizer
- 7:1LVDS编码 为LVDS方面需求的人提供参考设计，很高兴- This VHDL or Verilog source code is intended as a design reference which illustrates how these types of functions can be implemented. It is the user s responsibility to verify their design for consistency a
UART
- UART发送verilog源码，波特率115200，以及testbench源码-Send verilog source UART baud rate 115200, and testbench source
DS18B20ss
- 使用fpga硬件语言写的DS18B20程序，altera的fpga，单总线测试可用-altera fpga ds18b20
cop2000
- 模型机仿真的VHDL语言描述，在xilink9.1环境中实现。-VHDL simulation model of machine language to describe, in xilink9.1 environment implementation.
D_chufa
- 在QuartusII软件环境下，编写的移位寄存器的实现，包含仿真波形；-Quartusii software in the circumstances of the shift register, containing simulation waveforms
SAR-Signal-Simulation-of-FPGA-based-fast-way
- 基于FPGA的SAR回波仿真快速实现方法SAR Signal Simulation of FPGA-based fast way-SAR Signal Simulation of FPGA-based fast way
DNC12-test
- 128细分的步进电机驱动程序，有需要的朋友可以看看。-128 segments of the stepper motor driver, a friend in need can look at.
Virtex2_Manual
- Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, downlo
dll
- 在传输数字信号的时候，需要时钟定时，本程序可以从数据中恢复出时钟-In the transmission of digital signals, the need for clock timing, the program can recover a clock from the data