资源列表
verilog
- 介绍了一种64位子字并行乘法器的设计。根据不同的操作模式可以完成普通模式操作即64bit*64bit乘法操作，又可完成子字并行操作模式，即4个16bit*16bit乘法操作。-Introduced a 64-seat word parallel multiplier design. Depending on the operating mode Normal mode operation can be done that 64bit* 64bit multiplication operation
Verilog
- 无线通信FPGA 一书中的verilog代码- verilog core
VHDL-8259
- 用VHDL语言 实现8259A中断芯片的功能-VHDL language with the 8259A interrupt the function of the chip
pll
- quartusII环境下用Verilog语言的数字锁相环的实现。- In quartusII environment digital PLL implementation using Verilog language .
URISC
- 一个完整的带I/O和RAM，ROM的URISC,可以完成A+B/2的运算。实际上，通过对ROM的手工编程，可以实现8为数据的加减乘除，已经更加复杂的运算。-An ultimate URISC With I/Os, a RAM, a ROM,which can complete A+ B/2 calculations. In fact, through the ROM of the manual programming, it can do more calculations,such as A+
LCD12864_verilog
- FPGA 用VEILOG语言下写的LCD12864的驱动。已经调试通过！-FPGA with the language' s written LCD12864 VEILOG drive. Has been debugged!
mppt_mod
- maximum power point tracking system (MPPT) VHDL code with testbench
TCM
- Trellis coded modulation(TCM) VHDL code
xhdl_4.1.4_demo_patch
- this is X-HDL Crack. support xhdl_4.1.4
fpga1244131245d
- 基于FPGA的FIR数字滤波器的设计与实现。滤波器设计参数可实现17阶和32阶线性相位FIR滤波器-FPGA-based FIR digital filter design and implementation. Filter design parameters can be achieved on 17 order and 32 order linear phase FIR filter
program
- 1/100s计时器的FPGA实现，本设计的计时器能实现显示最长计时时间为1分59.99秒，且精度大于1/100s，计时器能显示1/100s的时间.-1/100s timer FPGA, the design of the timer to achieve the longest time show time of 1 minutes, 59.99 seconds, and the precision is greater than 1/100s, 1/100s timer can display
Clocking-resources-Spartan-6
- CLOCK RESOURCES FOR SPARTAN 6 LX150T.