资源列表
aes-core
- Verilog编写的美国标准加密算法AES的硬件实现包含完整代码及测试程序。- Verilog the compilation American standard encryption algorithm AES hardware realizes contains the complete code and the test order.
CY7c68013
- CY7c68013的读写程序,开发环境是ISE-CY7c68013 write and read program
chengfaqi
- 基于FPGA采用时序逻辑方法设计的16位乘法器代码-FPGA-based temporal logic designed using 16-bit multiplier code
Verilog_pingpang
- 其实乒乓操作用面积换速度，本文件是用verilog实现乒乓操作-In fact, with an area for ping-pong operation speed, this document is to achieve pong operation verilog
Adaptive-echo-cancellation
- 自适应回波消除，FPGA方面的设计论文，对大家有用的可以下下来-Adaptive echo cancellation, FPGA design aspects of paper, can be useful to all of us look down under
electronic-clock
- Verliog HDL数字系统设计项目，电子钟。该电子钟可以实现时钟、日期、闹钟、秒表功能。-Verliog HDL digital system design projects, electronic clock. The clock can clock, date, alarm clock, stopwatch function.
xapp250
- xilinx 关于时钟数据恢复中的源代码-xilinx on the clock and data recovery in the source code
icache
- ARM9指令Cache缓存模块的Verilog代码-cache verilog for ARM
UART_FIFO
- Verilog 语言描述，基于FIFO设计的UART。Quartus 10中编译通过-Verilog language descr iption, based on the design of the UART FIFO
RC
- 使用multisim仿真程序编写的RC消除噪声电路的仿真图-Multisim simulation program written using the RC circuit simulation to eliminate the noise figure
FPGA-drive-12864
- FPGA驱动12864液晶,一般可以显示我们想显示的，只要相应的适当修改。-The FPGA drive, can generally 12864 LCD display we want to show, as long as the corresponding appropriate modification.
LCD12864
- 基于 NIOS II的LCD12864 IP核设计，有了这个可以直接使用LCD12864-NIOS II of LCD12864 IP-based core design, with this can be used directly LCD12864