资源列表
TLV5619kongzhiDAC902defuduchengxu
- TLV5619控制DAC902的幅度程序-TLV5619 the magnitude of the control procedures DAC902
trafficlight
- 基于VHDL硬件描述语言的数字交通灯控制器的设计与实现-VHDL hardware descr iption language based on the number of traffic light controller design and implementation
ycbcr.v
- full pipelined RGB->YUV 420 converter, Xilinx/Altera implementable
vhdl-dianziwannianli
- 基于FPGA的电子万年历，此电子万年历系统主要有8个模块分别设计1. 主控制模块 maincontrol 2. 时间及其设置模块 timepiece_main 3. 时间显示动态位选模块 time_disp_select 4. 显示模块 disp_data_mux 5. 秒表模块 stopwatch 6. 日期显示与设置模块 date_main 7. 闹钟模块 alarmclock 8. 分频模块 fdiv -FPGA-based electronic calen
svpwm-programm-important
- SVPWM的英文程序，包括前期的详细理论分析，最后配有程序。非常好的参考。-SVPWM English procedures, including details of previous theoretical analysis, the last with a program. Very good reference.
dxp_intlib_by_myself
- 该软件包为dxp的集成元件库，本人整理的。方便大家使用-The integrated software package for the dxp library, I finishing. Convenience we use
LAB17
- 学校FPGA实验教学work1之十七讲，西欧啊次哦十六讲-Schools Experiment work1 the seventh FPGA say, oh sixteen times in Western Europe say ah
new_RS_Verilog
- 这是基于FPGA的RS编解码的实际例子。我已经调试完成！- This is arranges the decoding based on FPGA RS the actual example. I already debugged complete!
count
- 吉大短学期CPLD实习程序 可逆10 进制计数器，用1 位拨码开关进行加减控制：输入为0 时进行加计数，当输入为1 时进行减计数；用1 位拨码开关进行同步清零控制：输入为0 时清零，输入为1时正常计数。计数结果用数码管显示-Chittagong short term internship program CPLD reversible binary counter 10, with an addition and subtraction DIP switch control: when th
motor-positioning-control-vhdl
- 步进电机定位控制系统VHDL程序与仿真,绝对能用,经本人毕设测试!-Stepper motor positioning control system and simulation of VHDL program, absolutely can, after I completed the test set!
fir_lms
- verilog语言编写LMS（最小均方误差）自适应滤波器。-verilog language LMS (least mean square error) adaptive filter.
sqrt_Verilog
- Verilog实现开平方模块，内含有具体的算法描述Word文档，简单清晰明了。-sqrt with Verilog HDL. It is useful.