资源列表
meng
- for lattice s vhdl -for lattice s vhdl
notetabs
- 正弦波VHDL语言~~~ ~~~ ~~~`
tb_Test_CY7C1062AV33
- Test bench for CY7C1062AV-Test bench for CY7C1062AV33
behavioral_counter
- a simple behavioral counter handy for delay counters
11
- 时钟功能显示 包括闰年 每个月不同的天数-Clock function display includes a different number of days each month, leap year
digitron_driver_V
- 关于easy fpga开发板的led数码管的驱动； 此为verilog程序 --输入：控制端ctrl_digin[2:0]共三位，表示（0~7）控制8个数码管的选通， -- 数据端dig_dtin[3:0]共四位，表示（0~F）控制数码管显示的数字 -- 控制时钟clk_dig一位用于时钟同步 --输出：显示dig_dtout[6:0]共七位，控制A,B,C,D,E,F,G[6:0]小数点不包括在内； -- 控制位ctrl_digout[7:0]共八位，任意时
pnsequence.v
- pn sequence generator in verilog
anjianled
- 用按键控制流水灯一左移动亮起来，可自己修改成自己想要的型式-With a light water control buttons to move left lights up, you can make changes to the type you want to
netAD0809
- verilog描述的AD转换，简要的描述的AD转换的过程-verilog descr iption of AD
SignedMul18x18
- This my version of the scale, and the multiplier block, which can be used in digital devices-This is my version of the scale, and the multiplier block, which can be used in digital devices
MULT_ACC
- MULTIPLIER ACCUMULATOR, MAINLY FOR ILLUSTRATION, CAN BE USED TO IMPLEMENT DIGITAL FILTERS.
syncfifo
- 一个简单的基于single port ram 的同步fifo。只能支持只写或只读。-A simple single port ram based on the synchronization fifo. Can only support write-only or read-only.