资源列表
tb_ahb_master.rar
- this is a AMBA AHB code for master.,this is a AMBA AHB code for master.
bitNode_Behaviora_VHDL
- LDPC码的消息节点（Bitnode）消息更新过程的VHDL语言实现-LDPC code of the message node (Bitnode) news update process of the VHDL language
myAddSub
- Verilog adder for alu develpment
Lab4b_24897141
- this is vhdl behavorial model of a dct chip at an algorithmic level
eytruytf.u
- implementation of median filter
ANNA-Y
- 此源程序可包含verilog与vhdl任意倍数的分频，奇数偶数分频均可，均已通过验证，可直接使用。-The source code can contain multiple verilog and vhdl any frequency, both odd and even frequency, are validated and can be used directly.
spimaster
- 一般AD的spi配置代码，考虑的采样的时序问题。-General AD, spi configuration code, consider a sampling of the timing problems.
invsinwave
- vhdl code for inverse sine wave.
LANE0REGISTER
- The purpose of the Lane register is to get the TLPs or DLLPs from the Byte Striping Logic and to store the obtained data in the internal registers and then send the data to the scrambler and then get the Bit-by-Bit scrambled data from the Scrambler a
stop_watch
- 秒表设计,设计一个秒表计时器，具有全局清零信号和计数使能信号。-Stopwatch design, design a stopwatch timer, has a global reset signal and the count enable signal.
pipe_adder
- 使用流水结构设计的一个超前进位加法器，含测试文件-pipe adder
CMOS_interface
- CMOS Sensor 并行图像接收模块-CMOS Sensor input module