资源列表
3to8decoder
- 3 to 8 decoder is used to decode from 3 bit data to 8 bit data used in many applications
msk_top
- msk的verilog程序 利用ＦＰＧＡ实现
ad_in
- 用于FPGA,数据宽度转换。10位数据输入，经转换后128位输出模块。-For the FPGA, the data width conversion. 10-bit data input, the converted output module 128.
fifomodule
- 定义了一个FIFO和相关的读写功能,比较实用,可直接作为模块使用-define a FIFO that contains the relative read and write functions, and it can be used as module directly in ISE.
FIFO
- common FIFO module and it is easy to involve in ur design.
mlt
- --a0 a1 的输入我们用 k1 k2 代替 --b0 b1 的输入我们用 k3 k4 代替 --一开始数码管显示的是9.应为(11)*(11)就等于9 --数码管显示相减结?-- A0 a1 input we use the k1 k2 instead- b0 b1 input with k3 k4 instead- a digital display is 9. (11)* (11) is equivalent to 9- digital display subtract
shaomiaoqudongxianshidianlu
- 为了减少8位显示信号的接口连接线，实验箱中的数码显示采用扫描 显示工作模式。即8位数码管的七段译码输入（a,b,c,d,e,f,g）是并联在 一起的，而每一个数码管是通过一个3位选择sel[2..0]来选定 的。-In order to reduce the 8-bit display signal interface cable, digital display in the experimental box scan display mode of operation. I.e. the s
8bit_adder_AND_4x4_Multiplier
- 位加法器的verilog程序与4×4 乘法器的verilog描述-Verilog-bit adder of the procedures and 4 × 4 multiplier verilog descr iption! ! !
ADD_SUB_32bit
- 加减法器，可实现有无符号数的加减法-Modified instruments used, can be realized whether the number of addition and subtraction symbols
ram_tb
- ram vhdl module for modelsim and vhdl design
cic5r61
- 实现CIC5级滤波器功能。可以达到提亲一位或者延迟一采样的功能-Achieve CIC5 stage filter function.
carry-look-ahead-adder32
- This implements Carry look ahead adder in verilog