资源列表
statem
- 元件例化与层次设计,verilog 实例说明-components cases with the level of design, Verilog example
128×16ram
- VHDL程序设计的RAM存储器,双端口,128×16比特
add_ff8
- 利用触发器实现的,8位半加器的VHDL语言实现,适用于altera系列FPGA
PS2
- 设计一个计数器,信号频率为10MHZ,没10M个信号记一次数。-counter
1addto10
- 本程序是一个从1累加到10的小算法,用VHDL编写与实现-no
bingxingjiafa
- 用vhdl语言 来实现 四位并行加法器的功能 是本科生的必学内容
eda.rar
- 使用VHDL语言编程,烧录在芯片运行的倒数5秒响4声短铃最后一声长音的数字钟,The use of VHDL language programming, burn in the chip to run the last 5 seconds short bell ring 4 final say sound a long tone of digital clock
Clock_gen
- Vhdl clock generation Example source Input Clock 96Mhz Generated clock1 is Positive 300Khz clock & clock1 is Negative 300Khz clock -Vhdl clock generation Example source Input Clock 96Mhz Generated clock1 is Positive 300Khz clock & c
partiy-generator
- hi this is vhdl code for parity generator/checker
FSK
- FSK 的FPGA实现,使用verilogHDL语言-FSK in FPGA,using verilogHDL
IQ_sin_cos_mod
- Cordic根据输入的IQ正交两路信号求取对应的正切值-Cordic according to input the IQ of orthogonal signal to calculate the corresponding tangent value two road
lcdct
- at070tn83驱动 驱动 驱动 -driver of the lcd