资源列表
fpga-pwm
- 用verilog 语言写的FPGA子程序，环境是quartus II 7.2 已经在EP1C6Q240上测试过，源码包含仿真文件和仿真结果，本程序可以直接嵌入做子程序使用。-FPGA with the verilog language written subroutines, the environment is quartus II 7.2 has been tested on EP1C6Q240, source code contains the simulation files and s
edastudy
- 介绍EDA技术历史和现状及发展趋势，设计方法，其中包括一个小的例程-Describes the history and current status of EDA technologies and development trends, design methodology, which includes a small routine
pingpangchengxu
- 基于vhdl的实验仿真源码，包含完整的各项文件，是一个乒乓球游戏的小实验。-Linux embedded system based on the simulation source code, including the integrity of the document is a table tennis game is a small experiment.
mdio
- MDIO verilog RTL代码，SOC可以通过MDIO接口来访问外部PHY等慢速外设-MDIO verilog RTL code
1213
- 是十六位乘加器的VHDL语言描述。是我的课程设计。很好用。成绩是优秀-Is a sixteen by adder VHDL language descr iption. My course design. Good use. Performance is excellent
4位乘法累加器
- 4位乘法累加器，有需要的下吧，其他位的可以自行修改~-Multiplication accumulator 4
SRAM_Write_read
- SRAM读写的VHDL实验,通过对写入的数据与读出的数据进行比较,判断读写SRAM是否成功-SRAM read and write VHDL experiments on written data and read data to compare, to judge the success of SRAM read and write
R61526-initial-code
- initial code to set up the R61526 LCD controler
mux4_to_1
- 四选一选择器的Verilog HDL编程，在Quartus II中实现了四选一数据选择器的功能。-Four elected a selector Verilog HDL programming, in the Quartus II in the four election data selector function
DE2_NET
- 基于altera公司EP2C35672C6的DE2板子的光盘中的自带文件。DE2_NET，网络模块。-Based on the DE2 board altera company EP2C35672C6 CD in its own file. DE2_NET, network modules.
tlc5628VHDL
- VHDL实现对TLC5628 AD芯片的时序控制,vhdl对时序的控制不仅高速,而且控制时序清晰,容易实现-vhdl counter tlc5628
cpu
- 给定指令系统的处理器设计,指令字长16位，包含10种操作-Given instruction processor design, 16-bit instruction word length, contains 10 kinds of operations