资源列表
uart
- UART verilog 代码， 内置CPU接口方式，支持2线制和流控4线制。支持轮训和中断方式。-UART verilog source code
dds_verilog
- 产生信号发生器的dds的verilog代码，很好的学习资料，值得学习-Verilog code generated signal generator dds good learning materials, it is worth learning
2_10encode
- VHDL语言描述的二进制十进制译码电路，已经编译完成-Binary decimal decoder circuit
4bitALU
- 4 bit ALU 设计功能仿真和门级仿真结果 -4 bit ALU
RS232
- 基于FPGA利用程序实现串口RS232与电脑通信-RS232 serial port to communicate with the computer based on the the FPGA use of program
PiSo
- 8位并行输入的数转换成串行输出，是基于高级硬件编程语言VHDL编写的。-8-bit parallel input into serial output digital conversion is based on the high-level hardware programming language VHDL prepared.
Timing_Closure
- 一份FPGA布局布线的时序约束资料，中文描述-A FPGA placement and routing information on the timing constraints, the Chinese describe the
FIR
- Quartus II中滤波器的设计，里面含有高通滤波器，低通滤波器，带阻滤波器，主要用于滤除心电信号中的干扰-Quartus II filter design, which contains a high-pass filter, low-pass filter, band stop filter, mainly used for filtering of ECG signal interference
13_lcd
- verilog 实现 1602 液晶显示程序。 -a lcd project.It turns out good!
EthernetUDP
- ethernet mac core.this is the etherenet udp application
spi
- Verilog语言写的SPI接口（层次化设计，便于升级）-The implememt of SPI interface using Verilog HDL
EDA.DAC8812
- DAC8812英文资料，内容非常详细。真值表，时序图，电气特性等。-DAC8812 information in English, the content is very detailed.