资源列表
rrc_filter
- this is a verilog code for root raised cosine filter
love
- 用数码管和LED等来显示心形的LOVE，可以送给女朋友的 哦-LOVE heart-shaped digital control and LED display, can be given to a girlfriend
oc_mkjpeg
- Pure hardware JPEG Encoder design. Package includes vhdl source code, test bench, detail design document. Written in VHDL. Verified on Xilinx XC4VLX25. Rncode 320x240 bmp picture in 3ms at 50 quality, 100Mhz clock.-Pure hardware JPEG Encoder design.
2048Mb_ddr3
- 美光DDR3存储器模型，用verilog语言编写，通用模型-DDR3 MEMORY
eetop.cn_licgen_ise_13.1
- this the license genarator for xilinx ISE DESIGN SUIT 13.1 -this is the license genarator for xilinx ISE DESIGN SUIT 13.1
cic
- 一个很好的CIC滤波程序！可以直接使用!-CIC filter a very good program!
CMI
- 基于FPGA/CPLD的CMI编解码设计，含程序说明及仿真截图。-Based on FPGA/CPLD' s CMI codec design, including descr iption of the procedures and simulation screenshot.
led_shift
- 本程序代码实现了FPGA中的流水灯功能，可以控制向左还是向右循环点亮发光二极管。-The program code to achieve the water lights in the FPGA, you can control the left or right loop light emitting diode.
divider
- 用verilog编写的快速除法器（8位除以4位）-With the rapid verilog write except machines (eight divided by four)
EDA
- EDA实验序列信号检测器和模可变计数器，工程文件和VHDL文件-EDA test sequence signal detector and variable-counter model, project files and VHDL files
vga_top
- VGA测试程序顶层文件，为视频信号的处理提供框架-Top-level test program files VGA, for video signal processing to provide a framework
adc
- communication spi adc for spartan 3e