资源列表
miaobiao
- 基于VHDL环境下的秒表设计源代码 很好用的-Environment based on VHDL design source code stopwatch good use
VerilogHDL
- 用于FPGA和CPLD编译的VerilogHDL书-For FPGA and CPLD book compiled VerilogHDL
alaw
- 使用VHDL实现通信脉冲编码调制（PCM）中的a律转换，并实现串并、并串转换。-Use VHDL to achieve communication pulse code modulation (PCM) of a law conversion, and to achieve and string, and string conversion.
xapp529_6_1
- 一些有用的IP核，本人也是刚涉及FPGA到开发，特别希望前辈们能够共享一些关于图像处理方面的IP核-Some useful IP core, and I was just involved in FPGA to development, particularly the older generation to share some information about aspects of image processing IP core
xapp529_6_2
- 一些有用的IP核，本人也是刚涉及FPGA到开发，特别希望前辈们能够共享一些关于图像处理方面的IP核-Some useful IP core, and I was just involved in FPGA to development, particularly the older generation to share some information about aspects of image processing IP core
Vmeter
- 关于电压表的一个VHDL程序，能够成功实现，可共初学者学习-A voltage meter on the VHDL program to be successful in the realization of a total beginner can learn
006
- 基于FPGA实现的一种新型数字锁相环-Based on the FPGA realization of a new digital PLL
jiaotongdeng
- vhdl的铜须等-VHDL copper have to wait
VHDL
- 数字钟的设计，有时，分，秒，置数等功能。-Digital clock design, sometimes, minutes and seconds, buy a few functions.
shizhong
- 这个VHDL与其他上传的代码不同，这个代码更适合于初学者。电子时钟已经在硬件上得到成功仿真。-From the VHDL code with other different, the code is more suitable for beginners. Electronic clock has been successful in the hardware simulation.
logic
- 5位的操作数X和Y输入后暂存在寄存器A和B中，两位的操作控制码control暂存在寄存器C中，按照control码的不同，分布实现下列操作： 00控制X+Y 01控制X-Y 10控制X and Y 11控制 X xor Y 运算结果暂存在寄存器D中，然后输出。 -5 of the operand X and Y after the temporary importation of A and B in the register, the two operational c
AlteraFPGACPLD1
- Altera FPGA_CPLD设计 基础篇-Altera FPGA_CPLD Part Design