资源列表
multi
- 基于CPLD/FPGA的十六位乘法器的VHDL实现-Based on CPLD/FPGA multiplier of 16 to achieve the VHDL
ADC0809
- 用CPLD/FPGA驱动ADC0809芯片的VHDL源程序-Using CPLD/FPGA drive ADC0809 chip VHDL source
clock
- 基于VHDL的电子时钟设计-VHDL-based design of an electronic clock
seg_test
- 基于VHDL的序列检测器设计-VHDL-based sequence detector design
1
- 1位全加器的vhdl设计 通过两个半加起实现-A full adder of VHDL design increases since the adoption of two and a half to achieve
SHIYAN5
- IO设备vhdl语言1234556778892341-IO equipment VHDL language 1234556778892341
ALU
- 在Xilinx7.1平台下编写的ALU代码，可以实现五位加法、减法、与、异或四种运算！-Xilinx7.1 platform in the preparation of the ALU code, can be achieved five adder, subtraction, and, four computing XOR!
SSD2
- 在Xilinx7.1平台下编写，可以实现七段数码管的译码功能！-Xilinx7.1 platform in the preparation can be achieved and seventh of the decoding functions of digital tube!
I2C
- FPGA I2C
EEPROM
- VHDL语言写的IIC实现EEPROM，很好的程序，已经用过，没有问题-Written in VHDL language IIC achieve EEPROM, good procedures are used, there is no problem
uart2fli
- Modelsim FLI接口设计实例，适合学习Modelsim fli接口编程者学习。-Modelsim FLI interface design for learning Modelsim fli learn programming interface.
SPI-Collect
- 一个spi串口 希望大家能用上 -Spi serial a hope that we can use on