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newclock3
- 应用MaxplusII平台的数字时钟的VHDL源程序，可以解压后直接运行，已经过测试，希望对大家有所帮助。-Applied Digital Clock MaxplusII platform of VHDL source code can be run directly after decompression, has been tested, I hope all of you to help.
hdl
- cordic IC implement for fast cordic calculate. Including test bench. feature: 1. slicon proved. 2. support angle recored algorithm.-cordic IC implement for fast cordic calculate.Including test bench.feature: 1. slicon proved.2. support angle
1
- 序列信号的发生器 希望可以对大家有用处-Sequence signal generator for all of us hope that we can be useful
64_tlc
- 交通控制灯的控制设计 实现的功能基本齐全-Traffic control light control design to achieve an almost fully functional
VHDL
- VHDL很不错的教程 可以让你在一天之内理解VHDL语言 熟悉基本语法-VHDL is very good tutorial can let you in one day understand the VHDL language familiar with the basic grammar
speednew
- ISA板卡，CPLD原理图，altera maxII CPLD芯片。实现运动控制，标准安川伺服器控制接口。-ISA board, CPLD schematic, altera maxII CPLD chip. The realization of motion control, the standard control interface YASKAWA server.
38yima
- 本文为用vhdl语言编写的38译码器，为doc格式，请先复制到相应软件例如maxplus中再使用。-This article was prepared by using VHDL language decoder 38 for doc format, please copy to the appropriate software such as maxplus in the re-use.
husw
- 用VHDL语言设计维特比 解码器 是VHDL原代码用ModelSim XE III 6.3c软件实现仿真-Language Design with VHDL Viterbi decoder is the VHDL source code with ModelSim XE III 6.3c software simulation
cla4
- verilog code 4-bit carry look-ahead adder output [3:0] s //summation output cout //carryout input [3:0] i1 //input1 input [3:0] i2 //input2 input c0 //前一級進位-verilog code4-bit carry look-ahead adderoutput [3:0] s// summationoutput cout// c
cla16
- verilog code 16-bit carry look-ahead adder output [15:0] sum // 相加總和 output carryout // 進位 input [15:0] A_in // 輸入A input [15:0] B_in // 輸入B input carryin // 第一級進位 C0 -verilog code16-bit carry look-ahead adderoutput [15:0] sum// sum of
array_multiplier
- verilog code array_multiplier output [7:0] product input [3:0] wire_x input [3:0] wire_y -verilog codearray_multiplieroutput [7:0] product input [3:0] wire_x input [3:0] wire_y
SRT
- verilog code radix-2 SRT divider input [7:0]Dividend input [3:0]Divisor output [4:0]Quotient output [8:0]Remainder -verilog coderadix-2 SRT dividerinput [7:0] Dividend input [3:0] Divisor output [4:0] Quotient output [8:0] Remainde