资源列表
P
- 该工程实现了BDPSK调制器的设计，其中的主要模块有差分编码模块、分频模块、延时模块等。该工程在Quartus软件下运行。-The project implements the design of BDPSK modulator, the main module has a differential coding module, frequency module, time delay module etc.. The operation of the project in Quartus so
I2S-Serial-communication
- 这是I2S总线接口的Verilog实现源代码，包含了计数、左右通道选择、串行转并行等功能。-This is a Verilog I2S bus interface source code, including the count, about channel selection, serial to parallel functions.
CRC32_D8
- 循环冗余校验编码，CRC32，verilog实现，xilinx平台上验证，结果可用。-CRC coding, CRC32, verilog implementation, verification on xilinx platform, the results are available.
1---Serial-interface-(RS-232)
- Verilog HDL编写的RS232通信接口，包含RS232接口通信原理解析和编程实现文档-Verilog HDL prepared by the RS232 communication interface, including RS232 interface communication principles of parsing and programming documents
uart
- 根据黑金动力编写的vhdl版本uart，很适合初学者移植使用-According black gold vhdl written power version uart, very suitable for beginners transplant use
smg
- 根据黑金动力编写的数码管vhdl版本，适合初学者使用- According black gold vhdl power digital version written for beginners
ds1302
- 根据黑金动力编写的ds1302的vhdl程序，方便初学者对ds1302的学习-Ds1302 prepared according to the power of black gold vhdl procedures, easy for beginners to learn ds1302
i2c_6114
- 使用FPGA对NVP6114进行配置！绝对原创，已经成功应用到AHD高清监控机上。代码为纯VHDL编写，不是软核的。-Using FPGA to configure NVP6114! Absolutely original, has been successfully applied to the AHD high-definition monitor system. Write code for pure VHDL, not NIOS or MicroBlaze.
PV_Single_Phase_bingwang
- 包括PV模块，MPPT，并网系统， mdl格式，且是单相并网 。-Including PV modules, MPPT, grid system, MDL format, and is a single-phase grid.
keyscan
- verilog4*4键盘扫描代码源文件和工程，有消抖，已验证可用。可直接用quartus ii 打开-verilog4* 4 keyboard scan codes source file, there is debounced, verify available.
de2_115_sram
- 基于quartus13.1在DE2_115平台下进行了SRAM的测试开发，功能虽然简单，但是代码风格很好，封装性很好！应该学会模块化书写程序！-DE2 115 SRAM QUARTUS13.1
i2c_to_gpio
- 以lattice的FPGA作为从机，使用VHDL，通过IIC扩展GPIO口。压缩包内也有IIC协议的pdf。我已测试通过。-IIC to GPIO