资源列表
7_BLE_WIFI_Lab
- altera max10 wifi demo， 非常有参考意义-altera max10 wifi demo，it is very usefull wo designers
LCDqudongchengxu
- lcd的驱动程序，很有用的！非常好。想初学开发版的赶紧下吧-lcd driver, very useful! Very good. Beginner version of the hurry to develop it under
verilog_cookbook
- verilog语言编程例子，很多很好很全的例子，可供大家学习参考-verilog language programming examples, it is all a lot of good examples for them to learn from reference
CPU
- CPU的构造，采用veril语言 对计算机专业同学有用-CPU
uart
- 232串口，我见过的最好的一个VERILOG描述的串口程序-232, one of the best I' ve ever seen descr iption of the serial program VERILOG
verilog_learn
- 初学者学习verilog的很好范例，对于初学者或许有用，都是很经典的例子-Verilog for beginners to learn a good example, may be useful for beginners, are classic examples
counter
- 用Verilog HDL语言实现FPGA的频率等精度测量。（已经过验证）-Using Verilog HDL language, such as FPGA frequency measurement accuracy. (Has already been verified)
ISCAS`89基准电路下载（包括Verilog和VHDL格式）
- SCAS `89 基准电路下载，包括Verilog和VHDL格式。verilog格式30个文件：包括S1238、S13207等;(SCAS `89 benchmark circuit downloads, including Verilog and VHDL formats. Verilog format 30 files: including S1238, S13207 and so on;)
FPGA数字钟
- FPGA数字钟
FPGA-digital-clock-design
- 运用顶层设计思路设计好各个底层文件（VHDL代码），对各个底层文件进行功能仿真；采用原理图或者文本方法来实现顶层文件的设计，对顶层文件进行功能真仿真。在顶层文件功能仿真正确之后，把顶层文件下载到实验箱的FPGA里边去，验证电路功能是否正确。具体时间用6位数码管来显示，具有整点报时功能. -Designed various underlying file using top level design (VHDL code), on functional simulation of variou
Static-PLL
- 基于Actel开发平台的静态锁相环设计，verilog实现-Actel development platform based on the static PLL design, verilog realized
4bit-microprocessor
- This file is 4bit microprocessor that included a variety of modules like ALU,Progrem Counter and ACC etc It is to calculate 4bit binary Topblock is top level module.