资源列表
system
- 基于vhdl的简易数字频率计设计，已经经过调试，可直接使用-Vhdl based on a simple digital frequency meter design, have been debugging, can be directly used
4
- QUARTUS 的配置及调试 flv的 -Quartus flv configuration and commissioning of the
sin_generate
- FPGA的正弦函数发生器文件，实测，可用。-Sine function generator file, FPGA test, available.
d_latch
- 使用VHDL编写的D触发器的简单程序，实现其功能-Simple and practical program written in VHDL D flip-flop
1
- NUC1xx Preliminary 系列CPU文档 -NUC1xx Preliminary
example
- FPGA大量实例,仅供参考,适合新手学习-FPGA a large number of examples for reference only, suitable for novices to learn
Exp_5
- 数码管动态显示，可以将输入的按键值显示在数码管上。(Dynamic display of digital tube)
DE2_115_Default
- D2-115学习源码，功能配置，音频功能，LCD控制，视频同步产生器-Learning source D2-115, the functional configuration of the audio function, LCD control, video sync generator
trafficled
- 数字电路的交通灯设计，具有主道和旁道两个不同时间的控制处理，使用vhdl语言编译，附有完整的报告及代码，我没有对我的信息进行删除，是希望大家能够诚实的利用这个代码，提高自身本领。-Digital circuit design of a traffic light with a main road and bypass roads are two different time control processing, using vhdl language compiler, with full r
DCM
- xilinx SP605开发板的DCM模块验证程序，coreGen工具生成DCM核，由DCM完成时钟分频、倍频、移相等操作-xilinx SP605 development board DCM module validation program, coreGen tool to generate nuclear DCM, completed by the DCM clock divider, frequency, and shift operations equal
Transmitter
- 基于hdl的ofdm基带处理器发射机的设计与实现 包括 工作时钟 主控单元 导频插入 长短训练序列生成 data符号调制 循环前缀与加窗处理 IFFT/FFT 信道编码 扰码模块等-Hdl of ofdm transmitter baseband processor based design and implementation including work clock master unit pilot insertion length of the training sequence g
NAND_Flash_Interface_DF
- actel NAND Flash Interface Design Example